1. Field of the Invention
The present invention relates to a CMOS structure and, more particularly, to a low-cost CMOS structure with dual gate dielectrics and a method of forming the CMOS structure.
2. Description of the Related Art
A complimentary metal oxide semiconductor (CMOS) circuit is a circuit that includes one or more n-channel (NMOS) transistors as well as one or more p-channel (PMOS) transistors. Physically, the NMOS and PMOS transistors each have spaced-apart source and drain regions, which are separated by a channel region, and a gate that lies over and is insulated from the channel region by a gate dielectric.
The source and drain regions, which are formed in a well of the opposite conductivity type, each includes an extension region and a main region that touches the extension region. The main region has a heavier dopant concentration than the extension region. The well, in turn, includes the channel region, which is a surface region of the well that touches the gate dielectric, and a below-the-channel region that touches and lies below the channel region.
Semiconductor chips commonly include two types of CMOS circuits: core CMOS circuits which perform the functionality of the chip, and input/output (I/O) CMOS circuits which connect the core CMOS circuits to the outside world. The core CMOS circuits typically operate with supply voltages that are lower than the supply voltages that are used by the I/O circuits.
When the core CMOS circuits utilize supply voltages that are lower than the supply voltages utilized by the I/O CMOS circuits, the NMOS and PMOS transistors in the core CMOS circuits are physically formed to have gate dielectrics that are thinner than the gate dielectrics of the NMOS and PMOS transistors in the I/O CMOS circuits. As a result, a CMOS structure with dual gate dielectrics is a type of CMOS structure that includes NMOS and PMOS transistors with thin gate dielectrics, and NMOS and PMOS transistors with thick gate dielectrics.
There are three common approaches to forming a CMOS structure with dual gate dielectrics. In a first approach, which is the most economical, the NMOS transistors in the core CMOS circuits and the NMOS transistors in the I/O CMOS circuits are formed as identical structures, except for the gate dielectrics, where the NMOS transistors in the core CMOS circuits have thinner gate dielectrics than the NMOS transistors in the I/O CMOS circuits. Similarly, the PMOS transistors in the core CMOS circuits and the PMOS transistors in the I/O CMOS circuits are formed as identical structures, except for the gate dielectrics, where the PMOS transistors in the core CMOS circuits have thinner gate dielectrics than the PMOS transistors in the I/O CMOS circuits.
In the first approach, a mask is used to form the gate dielectrics with two different thicknesses. For example, gate dielectric layers can be grown on each well. The growth then continues until the gate dielectric layers have reached the thickness required by the NMOS and PMOS transistors in the core CMOS circuits.
Following this, a mask is formed on the top surfaces of the gate dielectric layers to cover and protect the gate dielectric layers that lie over the wells of the NMOS and PMOS transistors of the core CMOS circuits. The mask also exposes the gate dielectric layers that lie over the wells of the NMOS and PMOS transistors of the I/O CMOS circuits. After the mask has been formed, the exposed gate dielectric layers are further grown until the gate dielectric layers over the wells of the NMOS and PMOS transistors of the I/O CMOS circuits have reached the thickness required by the NMOS and PMOS transistors in the I/O CMOS circuits.
In a second approach to forming a dual gate structure, in addition to using a mask to form the gate dielectrics with two different thicknesses as in the first approach, a pair of p-well masks is also used to form the p-type wells of the NMOS transistors. The first p-well mask of the pair exposes a substrate region where the p-type wells of the NMOS transistors in the core CMOS circuits are to be formed. The second p-well mask of the pair, which is formed after the first p-well mask has been removed, exposes a substrate region where the p-type wells of the NMOS transistors in the I/O CMOS circuits are to be formed.
As a result, when acceptor-type impurity atoms are implanted through the first and second p-well masks to form the p-type wells, the atoms are implanted so that the average dopant concentration of the channel region of each of the NMOS transistors in the core CMOS circuits is greater than the average dopant concentration of the channel region of each of the NMOS transistors in the I/O CMOS circuits.
In addition, the acceptor-type impurity atoms are also implanted through the first and second p-well masks so that the dopant profile of the below-the-channel region of each of the NMOS transistors in the core CMOS circuits is substantially different than the dopant profile of the below-the-channel region of each of the NMOS transistors in the I/O CMOS circuits.
Further, a pair of n-well masks is also used to form the n-type wells of the PMOS transistors. The first n-well mask of the pair exposes a substrate region where the n-type wells of the PMOS transistors in the core CMOS circuits are to be formed. The second n-well mask, which is formed after the first n-well mask has been removed, exposes a substrate region where the n-type wells of the PMOS transistors in the I/O CMOS circuits are to be formed.
As a result, when donor-type impurity atoms are implanted through the first and second n-well masks to form the n-type wells, the atoms are implanted so that the average dopant concentration of the channel region of each of the PMOS transistors in the core CMOS circuits is greater than the average dopant concentration of the channel region of each of the PMOS transistors in the I/O CMOS circuits.
In addition, the donor-type impurity atoms are also implanted through the first and second n-well masks so that the dopant profile of the below-the-channel region of each of the PMOS transistors in the core CMOS circuits is substantially different than the dopant profile of the below-the-channel region of each of the PMOS transistors in the I/O CMOS circuits. Otherwise, in the second approach, the NMOS transistors in the core and the I/O CMOS circuits are formed at the same time, while the PMOS transistors in the core and the I/O CMOS circuits are also formed at the same time.
In a third approach to forming a dual gate structure, in addition to using a mask to form the gate dielectrics with two different thicknesses as in the first approach, a pair of n-extension masks is used to form the n-type source and drain extension regions of the NMOS transistors, counter dope the channel regions of the NMOS transistors in the I/O CMOS circuits, and optionally form any p-type halo or pocket regions.
The first n-extension mask of the pair exposes the gates and the p-type wells of the NMOS transistors in the core CMOS circuit, while the second n-extension mask of the pair exposes the gates and the p-type wells of the NMOS transistors in the I/O CMOS circuits. When the first n-extension mask is in place, donor-type impurity atoms are implanted into the p-type wells of the NMOS transistors in the core CMOS circuits. The implant forms spaced-apart n-type source and drain extension regions in each p-type well of the NMOS transistors of the core CMOS circuits. The donor-type impurity atoms are blocked from the p-type channel regions by the gates.
While the first n-extension mask remains in place, acceptor-type impurity atoms can be optionally implanted into the p-type wells of the NMOS transistors in the core CMOS circuits at a number of angles. The implant forms spaced-apart p-type halo or pocket regions in each p-type well of the NMOS transistors in the core CMOS circuits. The p-type halo or pocket regions in a p-type well touch the n-type source and drain extension regions and the p-type channel region that are in the p-type well. The implant energy is insufficient to penetrate through the gates into the channel regions.
After the first n-extension mask has been removed and the second n-extension mask has been put in place, donor-type impurity atoms are implanted into the p-type wells of the NMOS transistors in the I/O CMOS circuits. The implant forms spaced-apart n-type source and drain extension regions in each p-type well of the NMOS transistors in the I/O CMOS circuits. The donor-type impurity atoms are blocked from the p-type channel region by the gate.
While the second n-extension mask is still in place, donor-type impurity atoms are again implanted into the p-type wells of the NMOS transistors in the I/O CMOS circuits. This time, however, the donor-type impurity atoms are implanted with an implant energy that is sufficient to penetrate through the gates into the channel regions and counter dope the channel regions.
The introduction of donor-type impurity atoms into a channel region having only acceptor-type impurity atoms has the net effect of reducing the average dopant concentration of the acceptor-type impurity atoms in the channel region. In a counter doped channel region, the channel region has both acceptor-type and donor-type impurity atoms.
While the second n-extension mask of the pair remains in place, acceptor-type impurity atoms can be optionally implanted into the p-type wells of the NMOS transistors in the I/O CMOS circuits at a number of angles. The implant forms spaced-apart p-type halo or pocket regions in each p-type well of the NMOS transistors in the I/O CMOS circuits. The implant energy is insufficient to penetrate through the gates into the channel regions.
Further, a pair of p-extension masks is used to form the p-type source and drain extension regions of the PMOS transistors, counter dope the channel regions of the PMOS transistors in the I/O CMOS circuits, and optionally form any n-type halo or pocket regions. The first p-extension mask of the pair exposes the gates and the n-type wells of the PMOS transistors in the core CMOS circuit, while the second p-extension mask of the pair exposes the gates and the n-type wells of the PMOS transistors in the I/O CMOS circuits.
When the first p-extension mask is in place, acceptor-type impurity atoms are implanted into the n-type wells of the PMOS transistors of the core CMOS circuits. The implant forms spaced-apart p-type source and drain extension regions in each n-type well of the PMOS transistors in the core CMOS circuits. The acceptor-type impurity atoms are blocked from the n-type channel regions by the gates.
While the first p-extension mask remains in place, donor-type impurity atoms can be optionally implanted into the n-type wells of the PMOS transistors of the core CMOS circuits at a number of angles. The implant forms spaced-apart n-type halo or pocket regions in each n-type well of the PMOS transistors in the core CMOS circuits. The n-type halo or pocket regions in an n-type well touch the p-type source and drain extension regions and the n-type channel region that are in the n-type well. The implant energy is insufficient to penetrate through the gates into the channel regions.
After the first p-extension mask has been removed and the second p-extension mask has been put in place, acceptor-type impurity atoms are implanted into the n-type wells of the PMOS transistors of the I/O CMOS circuits. The implant forms spaced-apart p-type source and drain extension regions in each n-type well of the PMOS transistors in the I/O CMOS circuits. The acceptor-type impurity atoms are blocked from the n-type channel region by the gate.
While the second p-extension mask is still in place, acceptor-type impurity atoms are again implanted into the n-type wells of the PMOS transistors of the I/O CMOS circuits. This time, however, the acceptor-type impurity atoms are implanted with an implant energy that is sufficient to penetrate through the gates into the channel regions and counter dope the channel regions. The introduction of acceptor-type impurity atoms into a channel region having substantially only donor-type impurity atoms has the net effect of reducing the average dopant concentration of the donor-type impurity atoms in the channel region.
While the second p-extension mask of the pair remains in place, donor-type impurity atoms can be optionally implanted into the n-type wells of the PMOS transistors of the I/O CMOS circuits at a number of angles. The implant forms spaced-apart n-type halo or pocket regions in each n-type well of the PMOS transistors of the I/O CMOS circuits. The implant energy is insufficient to penetrate through the gates into the channel regions.
Otherwise, in the third approach, the NMOS transistors in the core and I/O CMOS circuits are formed at the same time, while the PMOS transistors in the core and I/O CMOS circuits are also formed at the same time. Although there are three common methods of forming a CMOS structure with dual gate dielectrics, there is a need for other low-cost methods of forming a CMOS structure with dual gate dielectrics.